1. Field of the Invention
The present invention relates to design tools used in development of application specific integrated circuit (ASIC) technology; and more particularly to techniques involved in performing timing analysis on circuit designs used in ASICs.
2. Description of Related Art
The development of ASICs is based on designs including basic circuit cells selected from a library which spans the spectrum from simple glue logic elements to more complex logic blocks to complex system level core circuits. One part of the design and production methodology used for this kind of development involves timing validation for the designed system. Timing validation for the system is a complex technical issue when the number of basic building blocks on an integrated circuit becomes large. With current designs commonly involving more than a million usable gates, the timing validation of such systems can utilize significant amounts of processor time and memory, and require complex computer systems.
Development and verification tools used in ASIC design usually implement a hardware description language such as VERILOG or VHDL.
These tools are provided by major electronic design automation vendors. Such design tools provide the functions necessary to take a design specified in the hardware description language from a design at the netlist level to working silicon. The functions include timing analysis tools, floor planning tools, layout tools, packaging tools, and more.
In the ASIC industry, timing analysis has been done based on data structures known as netlists. There are a number of industry standard formats for such netlists including the Netlist Description Format (NDL), the Electronic Data Interchange Format (EDIF), and VERILOG format. The netlist comprises a list of basic cells used in the design of the system, specifying interconnection among the cells. Connections between or among cells are known as nets. A circuit path through a system comprises a number of cells and the interconnecting nets for the circuit path.
In the prior art, a full timing gate level simulation is executed based on an entire netlist. This can be quite time consuming as mentioned above. Also, it requires that the designer of any particular circuit unit being incorporated into a larger system level integration make the netlist available for use by people designing with the circuit unit. This is undesirable because it can amount to a publication of information which would otherwise be maintained as a company trade secret.
Accordingly, in order to make timing analysis more efficient, and to protect the investment of circuit developers in the ASIC field, it is desirable to provide an alternative to the full netlist description of certain circuit blocks, which can nonetheless be used by customers for timing analysis.